Chris H. Kim - Citegraph

Author Info

Name	Affiliation	Papers
CHRIS H. KIM	Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA	137
Collaborators	Citations	PageRank
224	1769	171.09
Referers	Referees	References
3238	1410	659

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Publications (100 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids.	0	0.34	2022
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process	1	0.34	2022
A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors	0	0.34	2022
A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal	0	0.34	2022
Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited)	0	0.34	2022
An All BTI (N-PBTI, N-NBTI, P-PBTI, P-NBTI) Odometer based on a Dual Power Rail Ring Oscillator Array	0	0.34	2021
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control	0	0.34	2021
Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps	0	0.34	2020
22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor.	0	0.34	2020
An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm	1	0.37	2019
Investigating the Aging Dynamics of Diode-Connected MOS Devices Using an Array-Based Characterization Vehicle in a 65nm Process	0	0.34	2019
CorNET: Deep Learning framework for PPG based Heart Rate Estimation and Biometric Identification in Ambulant Environment.	5	0.45	2019
Biotranslator: Inferring R-Peaks From Ambulatory Wrist-Worn Ppg Signal	0	0.34	2019
Real-time HR Estimation from wrist PPG using Binary LSTMs.	0	0.34	2019
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits	0	0.34	2018
A 0.0094mm<sup>2</sup>/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording	0	0.34	2018
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer	0	0.34	2018
Key-Based Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered Mode-Based Design.	3	0.49	2018
A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities	3	0.40	2017
A DRAM based physical unclonable function capable of generating >10<sup>32</sup> Challenge Response Pairs per 1Kbit array for secure chip authentication	1	0.36	2017
Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements.	2	0.38	2017
R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices.	0	0.34	2017
Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit.	1	0.36	2017
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection.	5	0.49	2017
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection.	1	0.35	2016
Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis.	1	0.36	2016
Estimating delay differences of arbiter PUFs using silicon data.	6	0.53	2016
A 0.0054-mm 2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor	0	0.34	2016
A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor.	0	0.34	2016
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.	2	0.39	2016
A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients	5	0.54	2015
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications	3	0.44	2015
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier	1	0.36	2015
Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR)	2	0.44	2015
Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor	23	1.18	2015
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology	4	0.54	2015
A 8–14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology	0	0.34	2015
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals	1	0.37	2014
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations	0	0.34	2014
Improving STT-MRAM density through multibit error correction	13	0.66	2014
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications	2	0.43	2014
Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design	1	0.39	2014
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems.	5	0.49	2014
SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data	3	0.42	2014
True Random Number Generator circuits based on single- and multi-phase beat frequency detection	16	0.88	2014
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications	1	0.38	2013
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme.	8	1.16	2013
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal	0	0.34	2013
Process and Reliability Sensors for Nanoscale CMOS.	1	0.35	2012
Design Of Ring Oscillator Structures For Measuring Isolated Nbti And Pbti	5	0.87	2012

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