| A 56 GS/s 8-bit 0.011 mm<sup>2</sup> 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS | 0 | 0.34 | 2022 |
| Bridging the Physical and Digital Worlds in Data-Driven Systems | 0 | 0.34 | 2022 |
| Fair and Comprehensive Benchmarking of Machine Learning Processing Chips | 0 | 0.34 | 2022 |
| TinyML: Current Progress, Research Challenges, and Future Roadmap | 0 | 0.34 | 2021 |
| A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm<sup>2</sup> Switched-Capacitor DAC in 16-nm FinFET CMOS | 2 | 0.45 | 2021 |
| Stability Of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach | 0 | 0.34 | 2021 |
| Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools | 1 | 0.35 | 2021 |
| A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler | 5 | 0.45 | 2021 |
| An 800 nW Switched-Capacitor Feature Extraction Filterbank for Sound Classification | 0 | 0.34 | 2021 |
| F4 - Electronics for a Quantum World. | 0 | 0.34 | 2021 |
| A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory | 1 | 0.36 | 2021 |
| Mixed-Signal Computing for Deep Neural Network Inference | 5 | 0.53 | 2021 |
| A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology | 1 | 0.36 | 2021 |
| Wearable System Design using Intrinsically Stretchable Temperature Sensor | 0 | 0.34 | 2020 |
| A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS | 0 | 0.34 | 2020 |
| Design Considerations for External Compensation Approaches to OLED Display Degradation | 0 | 0.34 | 2020 |
| Distortion Analysis of $RC$ Integrators With Wideband Input Signals | 0 | 0.34 | 2020 |
| Implications of Finite Clock Transition Time for LPTV Circuit Analysis | 0 | 0.34 | 2020 |
| Sensory Particles with Optical Telemetry | 0 | 0.34 | 2020 |
| A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology | 0 | 0.34 | 2020 |
| A Spectrum-Sensing DPD Feedback Receiver With <inline-formula> <tex-math notation="LaTeX">$30\times$ </tex-math></inline-formula> Reduction in ADC Acquisition Bandwidth and Sample Rate | 0 | 0.34 | 2019 |
| Global Asymptotic Stability and Stabilization of Long Short-Term Memory Neural Networks with Constant Weights and Biases | 0 | 0.34 | 2019 |
| Rram-Based In-Memory Computing For Embedded Deep Neural Networks | 0 | 0.34 | 2019 |
| 5.3 A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection | 0 | 0.34 | 2019 |
| An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency | 0 | 0.34 | 2019 |
| A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording. | 2 | 0.35 | 2019 |
| Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview | 1 | 0.36 | 2019 |
| An Always-On 3.8 <inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS | 10 | 0.60 | 2019 |
| Memory-Optimal Direct Convolutions for Maximizing Classification Accuracy in Embedded Applications | 0 | 0.34 | 2019 |
| A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection | 0 | 0.34 | 2019 |
| An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. | 0 | 0.34 | 2018 |
| Toward Always-On Mobile Object Detection: Energy Versus Performance Tradeoffs for Embedded HOG Feature Extraction. | 2 | 0.37 | 2018 |
| BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS | 5 | 0.62 | 2018 |
| Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver. | 0 | 0.34 | 2018 |
| A 56 Gb/s 6 mW 300 um<sup>2</sup> inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS | 0 | 0.34 | 2018 |
| A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler | 0 | 0.34 | 2018 |
| A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. | 8 | 0.71 | 2017 |
| Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks. | 0 | 0.34 | 2017 |
| 27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI. | 1 | 0.41 | 2017 |
| A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting. | 0 | 0.34 | 2017 |
| A 14 bit, 30 MS/s, 38 mW SAR ADC Using Noise Filter Gear Shifting | 4 | 0.53 | 2017 |
| Foreword: Intelligent Chips for a Smart World | 0 | 0.34 | 2017 |
| A Mixer Front End for a Four-Channel Modulated Wideband Converter With 62-dB Blocker Rejection. | 5 | 0.42 | 2017 |
| Metastablility in SAR ADCs. | 1 | 0.41 | 2017 |
| An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOS | 6 | 0.55 | 2016 |
| Data converter reflections: 19 papers from the last ten years that deserve a second look. | 0 | 0.34 | 2016 |
| The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications. | 5 | 0.65 | 2016 |
| A 0.003 mm2 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE. | 0 | 0.34 | 2016 |
| An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion | 0 | 0.34 | 2016 |
| Convolutional Neural Networks using Logarithmic Data Representation. | 38 | 1.45 | 2016 |
