Name
Affiliation
Papers
RYUSUKE EGAWA
Tohoku Univ, Cybersci Ctr, Res Div Supercomp Syst, Sendai, Miyagi 980, Japan
70
Collaborators
Citations 
PageRank 
107
109
28.68
Referers 
Referees 
References 
231
813
396
Search Limit
100813
Title
Citations
PageRank
Year
Portability of Vectorization-aware Performance Tuning Expertise across System Generations00.342021
Opencl-Like Offloading With Metaprogramming For Sx-Aurora Tsubasa?00.342021
Xevolver: A code transformation framework for separation of system-awareness from application codes.00.342020
Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems.00.342020
Exploiting the Potentials of the Second Generation SX-Aurora TSUBASA00.342020
DeLoc: A Locality and Memory-Congestion-Aware Task Mapping Method for Modern NUMA Systems00.342020
An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems.00.342019
Performance Evaluation of Different Implementation Schemes of an Iterative Flow Solver on Modern Vector Machines00.342019
A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism00.342019
An OpenCL-Like Offload Programming Framework for SX-Aurora TSUBASA00.342019
Peachy Parallel Assignments (EduHPC 2019)10.402019
An Automatic MPI Process Mapping Method Considering Locality and Memory Congestion on NUMA Systems00.342019
The Impacts of Locality and Memory Congestion-aware Thread Mapping on Energy Consumption of Modern NUMA Systems00.342019
Use Of Code Structural Features For Machine Learning To Predict Effective Optimizations00.342018
Investigating the Effects of Dynamic Thread Team Size Adjustment for Irregular Applications00.342018
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches.10.442018
Risk Management of Heatstroke Based on Fast Computation of Temperature and Water Loss Using Weather Data for Exposure to Ambient Heat and Solar Radiation.00.342018
An energy-aware set-level refreshing mechanism for eDRAM last-level caches00.342018
A Failure Prediction-Based Adaptive Checkpointing Method with Less Reliance on Temperature Monitoring for HPC Applications.00.342018
Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs.00.342017
An Adaptive Demotion Policy for High-Associativity Caches.00.342017
Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE.20.512017
Designing an Open Database of System-Aware Code Optimizations00.342017
An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches00.342017
A Directive Generation Approach to High Code-Maintainability for Various HPC Systems.00.342017
An application-adaptive data allocation method for multi-channel memory00.342017
A Memory Congestion-Aware MPI Process Placement for Modern NUMA Systems20.432017
An Application-Level Incremental Checkpointing Mechanism with Automatic Parameter Tuning00.342017
Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units.00.342016
A Directive Generation Approach Using User-Defined Rules00.342016
Translation of Large-Scale Simulation Codes for an OpenACC Platform Using the Xevolver Framework.00.342016
A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE.00.342016
Flexii: A Flexible Insertion Policy For Dynamic Cache Resizing Mechanisms00.342015
Design of a 3-D stacked floating-point Goldschmidt divider00.342015
Migration of an Atmospheric Simulation Code to an OpenACC Platform Using the Xevolver Framework.30.482015
A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE.00.342015
An energy-efficient dynamic memory address mapping mechanism00.342015
On-chip checkpointing with 3D-stacked memories00.342014
An energy optimization method for vector processing mechanisms00.342014
An impact of circuit scale on the performance of 3-D stacked arithmetic units10.372014
Mvp-Cache: A Multi-Banked Cache Memory For Energy-Efficient Vector Processing Of Multimedia Applications00.342014
A Compiler-Assisted OpenMP Migration Method Based on Automatic Parallelizing Information10.402014
Design of a 3-D stacked floating-point adder.10.372013
A Capacity-Aware Thread Scheduling Method Combined With Cache Partitioning To Reduce Inter-Thread Cache Conflicts10.362013
A flexible insertion policy for dynamic cache resizing mechanisms10.362013
Design and evaluation of a media-oriented vector processor with a multi-banked cache memory10.362013
An out-of-order vector processing mechanism for multimedia applications00.342012
A capacity-efficient insertion policy for dynamic cache resizing mechanisms00.342012
A media-oriented vector architectural extension with a high bandwidth cache system00.342012
Abstract: Exploring Design Space of a 3D Stacked Vector Cache00.342012
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