Mohamed Hassan - Citegraph

Author Info

Name	Affiliation	Papers
MOHAMED HASSAN	Univ. of Waterloo, Waterloo, ON, Canada\|c\|	12
Collaborators	Citations	PageRank
9	60	5.22
Referers	Referees	References
126	287	191

Search Limit

100287

Publications (12 rows)

Collaborators (9 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems	1	0.35	2021
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems	0	0.34	2019
On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?	3	0.41	2018
Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities.	1	0.35	2018
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.	5	0.41	2018
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems.	9	0.54	2018
A Comparative Study of Predictable DRAM Controllers.	5	0.43	2018
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.	0	0.34	2018
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems	4	0.38	2017
MCXplore: An automated framework for validating memory controller designs.	5	0.41	2016
Reverse-engineering embedded memory controllers through latency-based analysis	4	0.45	2015
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems	23	0.81	2015

1