Name
Abstract | ||
|---|---|---|
With increasing complexity of sub-micron designs, transistor level power estimations and analyses have become a necessity. Power conscious synthesis and optimizations are critical aspect of design flow. These require a fast approach to estimate average power and predict the upper bound. A novel assertion based approach for predicting worst dynamic power dissipation is presented here. This technique models all signal correlations within the design. It maximizes loading conditions using assertions to predict max power. An elmore model is used for calculating delay-based power estimates. The technique allows for quick prediction of the power dissipated in the design, without loss of much accuracy. It does not need any elaborate circuit simulation iterations. The input pattern dependence is eliminated using the Monte Carlo approach. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ICVD.2000.812581 | VLSI Design |
Keywords | Field | DocType |
design flow,average power,transistor level dynamic power,sub-micron design,delay-based power estimate,fast approach,transistor level power estimation,max power,worst dynamic power dissipation,monte carlo approach,power conscious synthesis,packaging,upper bound,monte carlo methods,monte carlo,design optimization,transistors,voltage,power dissipation,integrated circuit design,low power electronics,vlsi | Computer science,Upper and lower bounds,Real-time computing,Electronic engineering,Design flow,Dynamic demand,Integrated circuit design,Maximum power principle,Transistor,Very-large-scale integration,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7695-0487-6 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Savithri | 1 | 0 | 0.34 |
| R. Venkatesan | 2 | 104 | 7.92 |
| S. Bhaskar | 3 | 0 | 0.68 |