Paper Info
Title
Redundancies and don't cares in sequential logic synthesis
Abstract
The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions.
Year
DOI
Venue
1990
10.1007/BF00134012
Journal of Electronic Testing: Theory and Applications
Keywords
DocType
Volume
don't cares,redundancies,synthesis for testability
Journal
1
Issue
Citations 
PageRank 
1
26
2.48
References 
Authors
7
3
Name
Order
Citations
PageRank
Srinivas Devadas186061146.30
Hi-Keung Y. Ma2262.48
A. Richard Newton3887125.01