Name
Abstract | ||
|---|---|---|
We present the design of the FX1000, a high performance single chip Gigabit Ethernet NIC. With a 64 bit, 66 MHz PCI bus interface the chip can maintain a throughput of 2 Gbps between memory and the network. The 64-bit address also allows the FX1000 to address very large system memory. In addition, it transmits and receives packets with minimal assistance from the CPU. Furthermore, the FX1000 performs TCP checksum calculation and IEEE 802.1q virtual LAN processing in hardware. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/CMPCON.1997.584711 | COMPCON |
Keywords | Field | DocType |
IEEE standards,local area networks,network interfaces,packet switching,performance evaluation,system buses,telecommunication standards,2 Gbit/s,64 bit,66 MHz,CPU,FX1000,IEEE 802.1q,PCI bus interface,TCP checksum calculation,high performance,network interface controller,packet sending,single chip Gigabit Ethernet NIC,very large system memory,virtual LAN processing | Carrier Ethernet,TCP offload engine,Computer science,Network packet,IEEE 802.1Q,Gigabit Ethernet,Virtual LAN,Network interface controller,Embedded system,Network interface | Conference |
ISSN | ISBN | Citations |
1063-6390 | 0-8186-7804-6 | 2 |
PageRank | References | Authors |
0.45 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Ross | 1 | 2 | 0.45 |
| A. Bechtolsheim | 2 | 2 | 0.45 |
| M. T. Le | 3 | 2 | 0.45 |
| J. O'Sullivan | 4 | 2 | 0.45 |