Paper Info
Title
Timing analysis challenges for high speed CPUs at 90nm and below
Abstract
Advances of the VLSI technology into the sub-90nm processes, enabling complex CPU designs that work at GHz frequencies pose numerous design and verification challenges.In this invited presentation, we focus on challenges in timing analysis of CPUs working at GHz speeds and sub-90nm processes.We start by brief overview of Timing Analysis tool used for intel CPUs and the "shell" timing models used for large blocks and how they integrate into full-chip model. Hierarchical timing is emphasized as key enabler for handling full-chip timing.Next, short-term challenges are presented:Xtalk impact on timingActive interconnectMixed abstraction, device to full-chipUse of domino as characterized cells.An intermediate accuracy model for Xtalk is introduced, called SMCF, which adaptively adjust equivalent MCF of attackers based on slope relationship and an empiric formula.We go into some detail with an example of timing checks that need to be applied for domino cells, which are different from checks applied on static cells.Finally some mid-term challenges are described:Multiple Input SwitchingProcess and environment variabilitySleep transistors.As variability is covered in more depth in other papers at this conference we mention it briefly but bring some examples of MIS and sleep transistor issues.
Year
DOI
Venue
2002
10.1145/589411.589420
Timing Issues in the Specification and Synthesis of Digital Systems
Keywords
Field
DocType
high speed cpus,hierarchical timing,timing analysis challenge,domino cell,full-chip timing,ghz speed,timing analysis,sub-90nm process,timing model,timing check,xtalk impact,ghz frequency,clock skew,chip
Clock network,Abstraction,Computer science,Domino,Clock skew,Static timing analysis,Transistor,Interconnection,Very-large-scale integration,Embedded system
Conference
ISBN
Citations 
PageRank 
1-58113-526-2
0
0.34
References 
Authors
1
2
Name
Order
Citations
PageRank
Avi Efrati100.68
Moshe Kleyner200.34