Title
High speed merged array multiplication
Abstract
Multiplication-accumulation operations described by $$\sum\nolimits_{k = 0}^{m - 1} {A_k B_k } $$ represent the fundamental computation involved in many digital signal processing algorithms. For high speed signal processing, one obvious approach to realize the above computation in VLSI is to employm discrete multipliers working in parallel. However, a more area efficient approach is offered by the merged multiplication technique [5]. But the principal drawback of the conventional merged technique is its longer latency than the former discrete approach. This work proposes a hardware algorithm for merged array multiplication which eliminates this drawback and achieves significant improvement in latency when compared with the conventional scheme for merged multiplication. The proposed algorithm utilizes multiple wave front computation as opposed to the traditional approach where computation in an array multiplier is carried out by a single wave front. The improvement in latency by the proposed approach is greater than 40% (form>2) when compared with a conventional approach to merged multiplication. The consequent cost in the form of additional requirement of VLSI area is found to be rather small. In this paper, we provide a thorough analytic discussion on the proposed algorithm and support it by experimental results.
Year
DOI
Venue
1995
10.1007/BF02407025
VLSI Signal Processing
Keywords
Field
DocType
Wave Front,Partial Product,Array Multiplication,Full Adder,Digital Signal Processing Algorithm
Signal processing,Wavefront,Adder,Latency (engineering),Computer science,Parallel computing,Theoretical computer science,Multiplier (economics),Multiplication,Very-large-scale integration,Computation
Journal
Volume
Issue
ISSN
10
1
0922-5773
Citations 
PageRank 
References 
1
0.43
3
Authors
2
Name
Order
Citations
PageRank
Farhad Fuad Islam110.43
Keikichi Tamaru212131.26