Title
An FPGA Implementation of the Linear Cryptanalysis
Abstract
Thispa per dealsw ith cryptographic concepts. It presents a hardware FPGA implementation of linear cryptanalysis of DES1. Linear cryptanalysis is the best attack known able to break DES faster than exhaustive search. Matsui's original attack [4, 5] could not be applied as such, and we had to implement a modified attack [1] to face hardware constraints. The resulting attack is less efficient than Matsui's attack, but fitsi n our hardware and breaksa DES key in 12-15 hourso n one single FPGA, therefore becoming the first practical implementation to our knowledge. As a comparison, the fastest implementation known so far used the idle time of 18 Intel Pentium III MMX, and broke a DES key in 4.32 days.Our fast implementation made it possible for us to perform practical tests, allowing a comparison with theoretical estimations.
Year
DOI
Venue
2002
10.1007/3-540-46117-5_87
FPL
Keywords
Field
DocType
fpga implementation,des key,best attack,fast implementation,practical implementation,hardware fpga implementation,original attack,linear cryptanalysis,modified attack,fastest implementation,resulting attack,fpga,cryptography,exhaustive search
MMX,Brute-force search,Computer science,Cryptography,Parallel computing,Field-programmable gate array,Cryptanalysis,Pentium,Linear cryptanalysis,Idle time
Conference
Volume
ISSN
ISBN
2438
0302-9743
3-540-44108-5
Citations 
PageRank 
References 
2
0.56
5
Authors
6
Name
Order
Citations
PageRank
François Koeune137152.80
Gaël Rouvroy229628.73
Francois-Xavier Standaert313513.05
Jean-Jacques Quisquater43894492.72
Jean-Pierre David520.56
Jean-Didier Legat653654.97