Name
Abstract | ||
|---|---|---|
Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods (such as BDD, Espresso or ABC System) and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits - Multiplier/Sorter and Parity/Majority circuits of variable input size. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CEC.2009.4983133 | IEEE Congress on Evolutionary Computation |
Keywords | Field | DocType |
gate-level optimization,cartesian genetic programming,benchmark circuit,abc system,polymorphic gate,efficient polymorphic circuit,polymorphic circuit,evolutionary optimization,polymorphic digital circuit,conventional design method,design optimization,polymorphism,cmos technology,optimization,digital circuits,data structures,design method,logic gates,genetic algorithms,design methodology,boolean functions,information technology,temperature,genetic programming,multiplexing | Boolean function,Data structure,Logic gate,Mathematical optimization,Digital electronics,Computer science,Parallel computing,Algorithm,Multiplier (economics),Multiplexing,Electronic circuit,Genetic algorithm | Conference |
ISBN | Citations | PageRank |
978-1-4244-2959-2 | 11 | 0.79 |
References | Authors | |
16 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zbysek Gajda | 1 | 66 | 6.30 |
| Sekanina Lukas | 2 | 343 | 32.35 |