Name
Abstract | ||
|---|---|---|
In this paper, an efficient technique for designing RAMs for on chip correction of double errors integrated on H-tree memory architecture is discussed. The reliability of the proposed design is improved by 8X while the Mean Time To Failure is improved 3X while comparing to traditional Hamming codes for a 256Mbits memory chip. The area is sacrificed for these reliability improvements, significant power savings and the performance boost. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/IOLTS.2007.37 | IOLTS |
Keywords | Field | DocType |
h-tree memory architecture,highly reliable power aware,performance boost,efficient technique,significant power saving,mean time,double error,reliability improvement,memory design,memory chip,proposed design,chip correction,hardware,integrated circuit design,error correction,computer science,hamming codes,ram,capacitance,hamming code,threshold voltage,mean time to failure,chip | Mean time between failures,Hamming code,Memory chip,Read-write memory,Computer science,Error detection and correction,Electronic engineering,Integrated circuit design,Energy consumption,Memory architecture | Conference |
ISSN | ISBN | Citations |
1942-9398 | 0-7695-2918-6 | 0 |
PageRank | References | Authors |
0.34 | 4 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Costas Argyrides | 1 | 91 | 11.20 |
| Dhiraj K. Pradhan | 2 | 231 | 21.80 |