Name
Abstract | ||
|---|---|---|
In this paper we propose an application of the Ant System (AS) to optimize combinational logic circuits at the gate level. We define a measure of quality improvement in partially built circuits to compute the distances required by the AS and we consider as optimal those solutions that represent functional circuits with a minimum amount of gates. The proposed methodology is described together with some examples taken from the literature that illustrate the feasibility of the approach. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-46406-9_3 | ICES |
Keywords | Field | DocType |
ant system,proposed methodology,quality improvement,minimum amount,combinational logic circuits,functional circuit,gate level,ant colony system,combinational logic circuit | Aerospace engineering,Combinational logic,Truth table,Crossover rate,Engineering,Electronic circuit,Ant colony,Computer engineering,Boolean expression,Genetic algorithm,Reliability engineering,Binary number | Conference |
Volume | ISSN | ISBN |
1801 | 0302-9743 | 3-540-67338-5 |
Citations | PageRank | References |
10 | 0.95 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. A. Coello Coello | 1 | 5799 | 427.99 |
| Rosa Laura Zavala Gutierrez | 2 | 34 | 6.11 |
| Benito Mendoza García | 3 | 34 | 4.53 |
| Arturo Hernández Aguirre | 4 | 405 | 58.10 |