Name
Abstract | ||
|---|---|---|
The quiescent current (IDDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of IDDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the IDDQ test. In this work, we present a method to estimate accurately the non-defective IDDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG (Automatic Test Pattern Generation) to obtain vectors having low/high defect-free IDDQ currents. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1023/A:1012215412601 | J. Electronic Testing |
Keywords | DocType | Volume |
I,DDQ,leakage current | Journal | 17 |
Issue | ISSN | ISBN |
3-4 | 1530-1877 | 0-7695-0701-8 |
Citations | PageRank | References |
1 | 0.34 | 12 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Antoni Ferré | 1 | 18 | 3.98 |
| Joan Figueras | 2 | 490 | 56.61 |