Paper Info
Title
Analysis and reliability test to improve the data retention performance of EPROM circuits
Abstract
Data retention lifetime is an important specification for the long term durability of EPROM circuits. While most of the published EPROM data retention results are based on empirical data, this paper presents an analytical approach which can be used to quantify EPROM data retention lifetime based on the circuit implementation. Two types of EPROM circuits are analyzed- a single transistor EPROM cell as well as a differential EPROM circuit. Using this new approach, the EPROM data retention performance is converted to a minimal residual gate charge requirement of the EPROM device which can then be used to directly compare and analyze the data retention performance of the EPROM circuits. The results of the analysis and comparison suggest that circuit implementation has great impact on EPROM data retention lifetime, and they also provide valuable insights on ways to improve the reliability of EPROM circuits. The analysis result of this paper on the differential EPROM circuit is further validated by wafer level reliability test (WLR) completed on an actual IC implementation, which suggests a good agreement between theoretical analysis and actual WLR data.
Year
DOI
Venue
2013
10.1109/ISQED.2013.6523622
ISQED
Keywords
Field
DocType
integrated circuit testing,long term durability specification,integrated circuit reliability,data retention lifetime,differential eprom circuit,non volatile memory,eprom data retention performance,wafer level reliability test,eprom,eprom data retention lifetime,wlr,reliability theory
Residual,Data retention,Durability,Computer science,Electronic engineering,Wafer level reliability,Transistor,EPROM,Electronic circuit
Conference
ISSN
ISBN
Citations 
1948-3287
978-1-4673-4951-2
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Jiyuan Luan100.68
Michael DiVita200.68