Name
Abstract | ||
|---|---|---|
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability to hide the latency of lengthy pipelines can significantly reduce the performance or impose unrealistic buffer requirements. Designs requiring reduction operations such as accumulation are particularly susceptible. In this paper we introduce two high-performance FPGA-based methods for reducing multiple sets of sequentially delivered floating-point values in optimal time without stalling the pipeline. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/FCCM.2005.42 | FCCM |
Keywords | Field | DocType |
multiple set,high-performance fpga-based method,algorithmic parallelism,pipelined core,fpga-based floating-point kernel,high-performance fpga-based general reduction,lengthy pipeline,performance advantage,general-purpose processor,floating-point value,optimal time,adders,floating point arithmetic,field programmable gate array,floating point,buffer overflow,field programmable gate arrays,steady state,crops,pipelines,design methodology,kernel,circuits | Kernel (linear algebra),Pipeline transport,Adder,Latency (engineering),Computer science,Floating point,Parallel computing,Field-programmable gate array,Real-time computing,Exploit,Buffer overflow | Conference |
ISBN | Citations | PageRank |
0-7695-2445-1 | 14 | 1.78 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gerald R. Morris | 1 | 165 | 14.45 |
| Ling Zhuo | 2 | 246 | 19.13 |
| Viktor K. Prasanna | 3 | 7211 | 762.74 |