Name
Abstract | ||
|---|---|---|
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time and power. The design approach considered in this paper allows the propagation of data from stage to stage to occur without the use of intermediate latches. Control signals are used to ensure that intermixing of data waves does not occur. The results of the study show that wave-pipelining helps to reduce the clock period. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/330855.330971 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
control signal,clock cycle time,ternary associative memory,router architecture,data wave,clock period,study show,design approach,wave-pipelining scheme,wave-pipelined router architecture,design,associative memory,cycle time,mems,verification,socs | Content-addressable memory,Computer science,Real-time computing,Ternary operation,Clock cycle time,Router architecture | Conference |
ISBN | Citations | PageRank |
1-58113-251-4 | 1 | 0.39 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| José G. Delgado-frias | 1 | 91 | 29.03 |
| Jabulani Nyathi | 2 | 21 | 6.36 |
| Laxmi N. Bhuyan | 3 | 2393 | 248.44 |