Name
Abstract | ||
|---|---|---|
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. In this paper, we present a global router that addresses the via number optimization problem throughout the entire global routing flow. We introduce the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. We integrate these three techniques into FastRoute 3.0 and achieve significant reduction in both via count and runtime. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ASPDAC.2009.4796542 | ASP-DAC |
Keywords | DocType | ISSN |
global routing stage,global routers,aware steiner tree generation,number optimization problem,critical factor,entire global routing flow,final circuit,cost function,global router,3-bend routing,benchmark testing,scheduling,steiner trees,optimization problem,steiner tree,integrated circuit design,vlsi,routing,network routing,metals | Conference | 2153-6961 |
Citations | PageRank | References |
66 | 2.30 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yue Xu | 1 | 159 | 9.34 |
| Yanheng Zhang | 2 | 152 | 8.05 |
| Chris Chu | 3 | 647 | 40.98 |