Title
Digital Inverse Timing Generator With Wide Dynamic Range
Abstract
This paper addresses a timing generator with an output inversely proportional to a binary input without involving cost/area intensive digital division hardware or DSP processor based solution. The timing generation is based on interpreting a binary input as a floating point number (step value) and successively accumulating it to a predefined count. A unique scaling process generates the step value required for accumulation from the binary input and also alleviates the requirement for a high clock frequency. The functionality of the proposed architecture was experimentally verified with implementation on an ALTERA CPLD EPF10K70 clocked at 25.175MHz. The dynamic range extends from 355ns to 17 mu s.
Year
DOI
Venue
2007
10.1109/ISCAS.2007.378398
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
Keywords
Field
DocType
pulse width modulation,floating point number,hardware,proportional control,dynamic range,floating point
Wide dynamic range,Complex programmable logic device,Dynamic range,Floating point,Computer science,Electronic engineering,Static timing analysis,Computer hardware,Scaling,Clock rate,Binary number
Conference
ISSN
Citations 
PageRank 
0271-4302
0
0.34
References 
Authors
3
2
Name
Order
Citations
PageRank
Bharath Balaji Kannan100.34
Khai D. T. Ngo200.34