Title | ||
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A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations |
Abstract | ||
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A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some prespecified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology. |
Year | DOI | Venue |
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2015 | 10.1109/ASPDAC.2015.7058984 | Design Automation Conference |
Keywords | Field | DocType |
mosfet,sram chips,circuit optimisation,energy conservation,energy consumption,integrated circuit design,8t sram cells,synopsys tcad tool suite,cell stability,circuit levels,cross-layer framework,deeply-scaled finfet devices,dual gate control feature,dual-gate controlled 6t sram cell,energy-efficient sram cells,leakage energy consumption,optimization,parametric yield,process variations,size 7 nm,spanning device,voltage 324 mv | Cross layer,Process corners,Computer science,Real-time computing,Static random-access memory,Electronic engineering,Parametric statistics,Cycles per instruction,Transistor,Energy consumption,Memory cell | Conference |
ISSN | Citations | PageRank |
2153-6961 | 0 | 0.34 |
References | Authors | |
11 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Alireza Shafaei | 1 | 155 | 15.01 |
Shuang Chen | 2 | 33 | 4.50 |
Yanzhi Wang | 3 | 94 | 10.82 |
Massoud Pedram | 4 | 7801 | 1211.32 |