Title
Hardware considerations in FFT processors
Abstract
In this paper some useful techniques have been given which simplify hardware of the complex multipliers, and reduce the memory required to store Fourier coefficients in FFT processors, with particular reference to the cascade organisation. It has been shown that significant saving in hardware results if the multiplications are done in sign-magnitude form while the other processing may be in 1's complement or 2's complement arithmetic. The multiplication in the propossd manner preserves the characteristics of 1's complement or 2's complement multiplications, as the case may be. The symmetry in a unit circle has been exploited to reduce the number of coefficients needed to store from N/2 to N/8 When this scheme is adopted, it allows a further saving in memory by 4 bits/complex word. In other words the memory required by a kth stage of an N(=2n)-point cascade FFT processor, with 2b-bits complex words, is reduced from bits to bits. It has been shown that a 16-point processor does not require any coefficient storage. The coefficients needed by the first stage of the 32-point cascade FFT processor may be generated simply using few gates.
Year
DOI
Venue
1976
10.1109/ICASSP.1976.1169957
Acoustics, Speech, and Signal Processing, IEEE International Conference ICASSP '76.
Keywords
Field
DocType
fourier coefficient,algorithm design and analysis,throughput,signal processing,hardware,digital filters
Signal processing,Algorithm design,Digital filter,Computer science,Arithmetic,Unit circle,Fast Fourier transform,Multiplication,Cascade,Throughput,Computer hardware
Conference
Volume
Citations 
PageRank 
1
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Agrawal, J.P.100.34
Jacob Ninan200.34