Title
Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW
Abstract
While FPGAs are mainly used for implementing general purpose logic circuits, the RHW works with the CPU to accelerate the computation intensive part of the application by reconfiguring its data paths and ALUs optimized for the algorithm. Hence the RRW was designed to implement multi-bit data paths and ALUs efficiently. We developed a new architecture that consists of a two-dimensional array of multi-bit original ALU that is composed of a type of adder with multi-functional pre-logics
Year
DOI
Venue
2000
10.1109/FPGA.2000.903921
Napa Valley, CA
Keywords
Field
DocType
adders,field programmable gate arrays,reconfigurable architectures,CPU,FPGA,RHW,adder,computation intensive,data path reconfiguration,general purpose logic circuits,mapping algorithms,multi-bit data path processing,multi-functional pre-logic,reconfigurable architecture,reconfigurable chip,two-dimensional array
Logic gate,Central processing unit,Adder,Computer science,Parallel computing,Field-programmable gate array,Chip,Application software,National Electrical Code,Computation
Conference
ISBN
Citations 
PageRank 
0-7695-0871-5
1
0.40
References 
Authors
1
4
Name
Order
Citations
PageRank
Tsukasa Yamauchi15310.15
Nakaya, S.210.40
Inuo, T.310.40
Nobuki Kajihara411616.37