Title
Enhanced multi-threshold (MTCMOS) circuits using variable well bias
Abstract
Advanced CMOS technology can enable high levels of performance with reduced active power at the expense of increased standby leakage, MTCMOS has previously been described as a method of reducing leakage in standby modes, by addition of a power supply interrupt switch. Enhancements using variable well bias and layout techniques are described and demonstrate increased performance and reduced leakage over conventional MTCMOS circuits
Year
DOI
Venue
2001
10.1109/LPE.2001.945394
Huntington Beach, CA
Keywords
Field
DocType
CMOS digital integrated circuits,integrated circuit layout,leakage currents,low-power electronics,active power,layout technique,leakage control,low-power digital circuit design,multi-threshold CMOS circuit,power supply interrupt switch,standby mode,variable well bias
Integrated circuit layout,Interrupt,Logic gate,Leakage (electronics),Standby power,Computer science,AC power,CMOS,Electronic engineering,Real-time computing,Low-power electronics
Conference
ISBN
Citations 
PageRank 
1-58113-371-5
33
6.81
References 
Authors
1
4
Name
Order
Citations
PageRank
Kosonocky, S.V.111223.08
Irnmediato, M.2336.81
Cottrell, P.3336.81
Hook, T.4336.81