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Abstract | ||
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ó We describe the implementation of a coarse-grain recongurable array that implements shift operations within its interconnection network. The connection point of such an array is a triangular matrix of switches. The recongurable array is geared toward the implementation of sequential Shift-and- Add algorithms. We show that a triangular switch-box that uses a level-restoring buffer with an unfolded multiplexer exhibits improved propagation delay and power consumption against prior art. This leads to a coarse-grain recongurable array that efciently implements transcendental functions. I. INTRODUCTION We present the VLSI implementation of a coarse-grain recongurable array that performs programmable shift op- erations within its interconnection network rather than its computing tiles. The connection point for a coarse-grain array is an N -by-N diagonal matrix of switches which we call a diagonal switch-box, where N is the word-length. To enable programmable shift within the interconnection network of such an array, we replace a diagonal matrix of switches with a triangular matrix of switches (a triangular switch-box). Since the triangular switch-box increases the capacitive load of the bus, the propagation delay and power consumption are larger than in the diagonal switch-box. We show that the level- restoring buffer with unfolded multiplexer (15) is very effec- tive at improving the electrical characteristics of the triangular switch-box. Overall, although the triangular switch-box has still slightly less performance than the diagonal switch-box, it implements the computation performed by a diagonal switch- box connected in series with a shift unit, which is embedded into most of the existing coarse-grain arrays. Simulations carried out with Cadence indicate that the triangular switch- box is 10% faster and consumes 9% less power than the best designs in the prior art. We also introduce a computing tile that performs two Shift-and-Add iterations per pipeline stage. The energy efcienc y of such a computing tile is 52 MOPS/mW, which is superior to the ones reported in the literature (13). Since these improvements come at the tiny area penalty, our approach is promising. The paper contributions are as follows. 1) Replaces a diagonal switch-box with a triangular switch- box to perform shift operations within the array's inter- connection network. 2) Introduces a circuit technique to build shift-enabled |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISCAS.2008.4541679 | Seattle, WA |
Keywords | Field | DocType |
VLSI,reconfigurable architectures,VLSI,coarse-grain reconfigurable array,level-restoring buffer,sequential shift-and-add algorithm,triangular switch-box | Reconfigurable array,Propagation delay,Computer science,Transcendental function,Multiplexer,Electronic engineering,Interconnection,Triangular matrix,Very-large-scale integration,Power consumption | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-1684-4 | 2 |
PageRank | References | Authors |
0.40 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Miller | 1 | 12 | 2.52 |
| Mihai Sima | 2 | 95 | 16.66 |
| Michael Mcguire | 3 | 80 | 9.79 |