Title
Analysis and optimization of sequential circuit element to combat single-event timing upsets
Abstract
This paper presents the analysis and optimization of a flip-flop while considering the effect of energetic particle hits on its setup and hold times. First it is shown that the particle hit tightens the setup and hold timing constraints imposed on the flip-flop. Next it is shown how to size transistors of a clocked master-slave CMOS flip-flop to make it more robust against single-event timing upsets. Experimental results to assess the effectiveness of transistor sizing step are provided and discussed.
Year
DOI
Venue
2010
10.1109/ISCAS.2010.5537377
Circuits and Systems
Keywords
Field
DocType
CMOS digital integrated circuits,flip-flops,sequential circuits,energetic particle hits,hold timing constraints,master-slave CMOS flip-flop,sequential circuit elements,setup timing constraints,single-event timing upsets
Sequential logic,Computer science,CMOS,Electronic engineering,Transistor sizing,Transistor
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-4244-5309-2
0
PageRank 
References 
Authors
0.34
7
3
Name
Order
Citations
PageRank
Hamed Abrishami100.34
Safar Hatami2112.13
Massoud Pedram378011211.32