Title
Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems
Abstract
This paper presents a reconfigurable Fast Fourier Transform (FFT) hardware architecture for 3GPP LTE systems. In the main FFT computing process, a novel processing kernel engine is proposed to support four configuration types of changeable hybrid-radix FFT operations. Also, in the data storage manipulation, a smart 2D-FIFO structure is used to flexibly handle efficient reading/writing data access for 36 different FFT sizes. In addition to a field-programmable gate array prototyping design approach, we provide application-specific integrated circuit implementation via TSMC 90-nm CMOS technology. The developed FFT chip only occupies a core area of 1.416mm2, consumes 24.2 mW of power, and reaches maximum speed of 111.11 MHz.
Year
DOI
Venue
2018
10.1016/j.icte.2017.11.007
ICT Express
Keywords
DocType
Volume
Reconfigurable,Hybrid radixes,2D FIFO,Fast Fourier transform,3GPP LTE
Journal
4
Issue
ISSN
Citations 
3
2405-9595
0
PageRank 
References 
Authors
0.34
3
2
Name
Order
Citations
PageRank
Xin-Yu Shih193.93
Hong-Ru Chou282.90