Abstract | ||
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The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet packets. Due to higher throughput and shorter delays, these solutions are considered as a major key to improving the quality of services. Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput. The proposed architectures, however, cannot reach a compromise among power consumption, memory usage, and throughput rate. In view of this, the architecture proposed in this paper contains a pipeline-based micro-core that is used in network processors to classify packets. To this end, three architectures have been implemented using the proposed micro-core. The first architecture performs parallel classification based on header fields. The second one classifies packets in a serial manner. The last architecture is the pipeline-based classifier, which can increase performance by nine times. The proposed architectures have been implemented on an FPGA chip. The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput. The architecture has a power consumption of is 1.294w, and its throughput with a frequency of 233 MHz exceeds 147 Gbps. |
Year | DOI | Venue |
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2022 | 10.1016/j.dcan.2022.04.010 | Digital Communications and Networks |
Keywords | DocType | Volume |
Efficiency,Intelligent flow processing,IoT,Packet classification,Pipeline | Journal | 8 |
Issue | ISSN | Citations |
4 | 2352-8648 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Seyed Navid Mousavi | 1 | 0 | 0.34 |
Fengping Chen | 2 | 0 | 0.34 |
Mahdi Abbasi | 3 | 4 | 1.42 |
Mohammad R. Khosravi | 4 | 26 | 7.55 |
Milad Rafiee | 5 | 0 | 0.34 |