| A 2.5-Gb/s Multi-Rate 0.25-<formula><tex>$\mu$</tex></formula>m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition | 14 | 1.43 | 2006 |
| Stability Analysis of the Second Order Sigma-Delta Modulator | 7 | 1.11 | 1994 |
