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SHENGCHENG WANG
Author Info
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Name
Affiliation
Papers
SHENGCHENG WANG
Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
12
Collaborators
Citations
PageRank
10
13
4.29
Referers
Referees
References
62
354
160
Search Limit
100
354
Publications (12 rows)
Collaborators (10 rows)
Referers (62 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Defect Clustering-Aware Spare-TSV Allocation in 3D ICs for Yield Enhancement
1
0.37
2019
Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs.
1
0.37
2018
Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.
0
0.34
2018
Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs.
1
0.36
2017
Recovery-aware proactive TSV repair for electromigration in 3D ICs.
0
0.34
2017
Leveraging recovery effect to reduce electromigration degradation in power/ground TSV.
0
0.34
2017
Thermal-Aware Tsv Repair For Electromigration In 3d Ics
4
0.40
2016
Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs
0
0.34
2016
Deadspace-aware Power/Ground TSV planning in 3D floorplanning
0
0.34
2015
Defect Clustering-Aware Spare-TSV Allocation for 3D ICs
2
0.37
2015
Stress-aware P/G TSV planning in 3D-ICs
1
0.35
2015
P/G TSV planning for IR-drop reduction in 3D-ICs
3
0.37
2014
1