| Analyzing and simulating fracture patterns of theran wall paintings | 2 | 0.35 | 2012 |
| Analyzing Fracture Patterns in TheranWall Paintings | 0 | 0.34 | 2010 |
| Isomorphism as technology transfer | 0 | 0.34 | 2005 |
| Frugality in path auctions | 72 | 7.23 | 2004 |
| Signal Standardization in Collision-based Soliton Computing. | 1 | 0.49 | 2004 |
| Agent-based simulation of dynamic online auctions | 22 | 3.81 | 2000 |
| Functional Algorithm Simulation of the Fast Multipole Method: Architectural Implications. | 6 | 0.70 | 1996 |
| When Can Solitons Compute? | 2 | 0.40 | 1996 |
| Implementation of Parallel Arithmetic in a Cellular Automaton | 3 | 0.46 | 1995 |
| A Comparison Study of Heuristics for Mapping Parallel Algorithms to Message-Passing Multiprocessors | 1 | 0.35 | 1995 |
| Optimization of wireless resources for personal communications mobility tracking | 117 | 46.86 | 1995 |
| Usage-based pricing of packet data generated by a heterogeneous user population | 11 | 2.50 | 1995 |
| Discrete-time signal design for maximizing separation in amplitude | 2 | 0.61 | 1995 |
| FAST: a functional algorithm simulated testbed | 12 | 1.11 | 1994 |
| Programmable Parallel Arithmetic in Cellular Automata Using a Particle Model. | 7 | 0.79 | 1994 |
| A comparison of two application-specific architectures for 2-d mesh computations | 0 | 0.34 | 1994 |
| A comparison of techniques used for mapping parallel algorithms to message-passing multiprocessors | 5 | 0.62 | 1994 |
| Reconfigurability and reliability of systolic/wavefront arrays | 1 | 0.38 | 1993 |
| Maintaining bipartite matchings in the presence of failures | 2 | 0.42 | 1993 |
| Two-Dimensional FHP Lattice Gases Are Computation Universal. | 0 | 0.34 | 1993 |
| Message Ordering In Multiprocessors With Synchronous Communication | 2 | 0.44 | 1992 |
| Error detection in arrays via dependency graphs | 1 | 0.41 | 1992 |
| Run-time error detection in arrays based on the data-dependency graph | 0 | 0.34 | 1992 |
| Suppression of near- and far-end crosstalk by linear pre- and post-filtering | 59 | 76.39 | 1992 |
| METEOR: a constraint-based FIR filter design program | 36 | 9.23 | 1992 |
| Explicit construction for reliable reconfigurable array architectures | 0 | 0.34 | 1991 |
| Comparison of tree and straight-line clocking for long systolic arrays | 6 | 0.99 | 1991 |
| Reconfigurability And Reliability Of Systolic Wave-Front Arrays | 0 | 0.34 | 1991 |
| Testing parallel simulators for two-dimensional lattice-gas automata | 1 | 0.41 | 1991 |
| Optimization of signal sets for partial-response channels. I. Numerical techniques | 8 | 1.58 | 1991 |
| Comparison of tree and straight-line clocking for long systolic arrays. | 0 | 0.34 | 1991 |
| A practical runtime test method for parallel lattice-gas automata | 0 | 0.34 | 1990 |
| Bubbles can make self-timed pipelines fast | 37 | 3.94 | 1990 |
| Multichannel signal processing for data communications in the presence of crosstalk | 35 | 16.18 | 1990 |
| Bounds on maximum throughput for digital communications with finite-precision and amplitude constraints | 4 | 2.47 | 1990 |
| A semiring on convex polygons and zero-sum cycle problems | 14 | 4.66 | 1990 |
| A filter compiler for digital sound synthesis | 0 | 0.34 | 1990 |
| An Upper Bound on Expected Clock Skew in Synchronous Systems | 9 | 1.23 | 1990 |
| Embedding Computation in One-Dimensional Automata by Phase Coding Solitons | 14 | 8.29 | 1988 |
| Planarity Testing Of Doubly Periodic Infinite-Graphs | 5 | 1.83 | 1988 |
| Finite-record filtering for bandlimited signals | 0 | 0.34 | 1987 |
| Testing for Cycles in Infinite Graphs with Periodic Structure (Extended Abstract) | 9 | 1.69 | 1987 |
| Performance of VLSI Engines for Lattice Computations | 1 | 0.49 | 1987 |
| Testability Conditions for Bilateral Arrays of Combinational Cells | 28 | 2.08 | 1986 |
| A fast tally structure and applications to signal processing. | 0 | 0.34 | 1984 |
| Design of FIR filters with flatness constraints. | 5 | 3.24 | 1983 |
| Unifying VLSI Array Designs with Geometric Transformations | 61 | 12.35 | 1983 |
| A VLSI layout for a pipelined Dadda multiplier | 25 | 6.94 | 1983 |
| Optimal choice of intermediate latching to maximize throughput in VLSI circuits | 7 | 5.12 | 1983 |
| Synthesis of timbral families by warped linear prediction | 4 | 1.05 | 1981 |
