Name
Abstract | ||
|---|---|---|
In this paper, we present an advanced multiprocessor cache architecture for chip multiprocessors (CMPs). It is designed for the scalable GigaNetIC CMP, which is based on massively parallel on-chip computing clusters. Our write-through multiprocessor cache is configurable in respect to the most relevant design options. It is supposed to be used in universal co-processors as well as in network processing units. For an early verification of the software and an early exploration of various hardware configurations, we have developed a SystemC-based simulation model for the complete chip multiprocessor. For detailed hardware-software co-verification, we use our FPGA-based rapid prototyping system RAPTOR2000 to emulate our architecture with near-ASIC performance. Finally, we demonstrate the performance gains for different application scenarios enabled by the usage of our multiprocessor cache. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1007/978-3-540-71270-1_7 | ARCS |
Keywords | Field | DocType |
fpga-based rapid prototyping system,multiprocessor cache,advanced multiprocessor cache architecture,chip multiprocessors,write-through multiprocessor cache,complete chip multiprocessor,near-asic performance,parallel soc architecture,early verification,performance gain,early exploration,simulation model,chip | Massively parallel,Cache,Computer science,CPU cache,Parallel computing,Symmetric multiprocessor system,Cache-only memory architecture,Real-time computing,Multiprocessing,SystemC,Design space exploration | Conference |
Volume | ISSN | Citations |
4415 | 0302-9743 | 1 |
PageRank | References | Authors |
0.43 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorg Christian Niemann | 1 | 63 | 6.65 |
| Christian Liß | 2 | 2 | 1.14 |
| Mario Porrmann | 3 | 420 | 50.91 |
| U. Rückert | 4 | 755 | 103.61 |