Name
Abstract | ||
|---|---|---|
The Steiner tree is a fundamental concept in automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner trees. The best solution in a statistical sense is obtained for any given set of N points. Experiments show that our results are better than those by previous techniques and are very close to the optima |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ASPDAC.2002.994967 | VLSI Design |
Keywords | Field | DocType |
integrated circuit interconnections,network routing,vlsi interconnect design,fundamental problem,trees (mathematics),probabilistic analysis,statistical analysis,statistical sense,circuit optimisation,network topology,rectilinear steiner trees,vlsi design,circuit layout cad,probabilistic analysis method,vlsi,steiner tree,best solution,signal nets,integrated circuit layout,rectilinear steiner tree,previous technique,automatic interconnect optimization,topology construction,probability,n point,routing,tree data structures,design optimization,very large scale integration,logic synthesis,topology | Logic synthesis,Integrated circuit layout,Steiner tree problem,Computer science,Network routing,Tree (data structure),Network topology,Electronic engineering,Probabilistic analysis of algorithms,Very-large-scale integration | Conference |
ISBN | Citations | PageRank |
0-7695-1441-3 | 0 | 0.34 |
References | Authors | |
4 | 1 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chunhong Chen | 1 | 176 | 15.66 |