Name
Abstract | ||
|---|---|---|
This paper proposes self-selection pseudo- circuit (SP), a simple and effective approach to increase switch connection reusing rate and improve the network performance. It especially suits the network in which the performance is dominated by the number of hops. In SP scheme, multiple switch connections are allowed to be reserved for one inport, and the flit can reuse the partial switch connection(s) based on the routing information. For the evaluation with the traces from Splash-2, SP reduces the interconnection latency by up to 21.6% (16.9% average) with 16-core CMP configuration, and 22.2% ( 19.5 on average) with 64- core CMP configuration. Evaluated with synthetic traffic, the proposed scheme decreases the latency up to 19% ( 16% average). |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/elex.9.558 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
interconnection architecture, Network-on-Chip | Interconnection architecture,Latency (engineering),Reuse,Computer science,Parallel computing,Network on a chip,Electronic engineering,Interconnection,Crossbar switch,Network performance | Journal |
Volume | Issue | ISSN |
9 | 6 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenmin Hu | 1 | 25 | 3.11 |
| Hengzhu Liu | 2 | 86 | 23.28 |
| Zhonghai Lu | 3 | 1063 | 100.12 |
| Axel Jantsch | 4 | 1875 | 169.83 |
| Guitao Fu | 5 | 0 | 1.01 |