Name
Abstract | ||
|---|---|---|
Hardware architectures based on a field of hardware-extended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance.Additionally, finding the optimal mapping can be a time-consuming task. We present a multiprocessor architecture along with a suitable design method that includes an automatedsolution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/DATE.2004.1268970 | DATE |
Keywords | Field | DocType |
high degree,mapping strategy,multiprocessor architecture,hardware-extended processor,hardware architecture,execution unit,resource-efficient network processing,future integration technology,flexible computing power,multiprocessor socs,optimal mapping,great impact,mapping problem,mobile network,network on chip,design method,system on chip,ad hoc networks,linear programming,integer programming,parallel processing,scheduling | Scheduling (computing),Computer science,Real-time computing,Integer programming,Wireless ad hoc network,Computer architecture,System on a chip,Parallel computing,Network packet,Multiprocessing,Embedded system,Hardware architecture,Scalability | Conference |
ISBN | Citations | PageRank |
0-7695-2085-5 | 3 | 0.39 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Grünewald | 1 | 115 | 10.64 |
| Jorg Christian Niemann | 2 | 63 | 6.65 |
| Mario Porrmann | 3 | 420 | 50.91 |
| U. Rückert | 4 | 755 | 103.61 |