Title
Message Dispatch on Pipelined Processors
Abstract
Object-oriented systems must implement message dispatch efficiently in order not to penalize the object-oriented programming style. We characterize the performance of most previously published dispatch techniques for both statically- and dynamically-typed languages with both single and multiple inheritance. Hardware organization (in particular, branch latency and superscalar instruction issue) significantly impacts dispatch performance. For example, inline caching may outperform C++-style "vtables" on deeply pipelined processors even though it executes more instructions per dispatch.We also show that adding support for dynamic typing or multiple inheritance does not significantly impact dispatch speed for most techniques, especially on superscalar machines. Instruction space overhead (calling sequences) can exceed the space cost of data structures (dispatch tables), so that minimal table size may not imply minimal run-time space usage.
Year
Venue
Keywords
1995
ECOOP
instruction space overhead,minimal run-time space usage,impact dispatch speed,message dispatch,space cost,impacts dispatch performance,pipelined processors,multiple inheritance,object-oriented programming style,minimal table size,dispatch technique,performance,computer architecture,dynamic typing,implementation,data structure,object oriented programming
Field
DocType
Volume
Data structure,Late binding,Double dispatch,Programming language,Computer science,Multiple dispatch,Parallel computing,Programming style,Time-driven programming,Inline caching,Multiple inheritance
Conference
952
ISSN
ISBN
Citations 
0302-9743
3-540-60160-0
22
PageRank 
References 
Authors
2.22
24
3
Name
Order
Citations
PageRank
Karel Driesen120516.32
Urs Hölzle23492346.29
Jan Vitek3797.76