Name
Abstract | ||
|---|---|---|
We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access. |
Year | Venue | Keywords |
|---|---|---|
1994 | ASYNC | memory design,high-level language specification,memory array,asynchronous circuit,timing consideration,pre-fetch mechanism,model energy consumption,low-energy asynchronous memory design,smaller array,cache memory,high level language,energy dissipation,application software,power dissipation,circuits,performance,voltage |
Field | DocType | Citations |
Registered memory,Interleaved memory,Semiconductor memory,Extended memory,Uniform memory access,Computer science,Non-uniform memory access,Flat memory model,Computer hardware,Computer memory | Conference | 3 |
PageRank | References | Authors |
4.41 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jose A. Tierno | 1 | 92 | 8.99 |
| Alain J. Martin | 2 | 1095 | 336.96 |