Name
Abstract | ||
|---|---|---|
In this article, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before fabricating the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with various performance and throughput requirements at high reliability. Furthermore, the composition based on predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators. Finally, we compare implementations of our architecture with state-of-the-art desktop CPUs. We use simple, general-purpose applications as well as the introduced packet processing tasks to determine the performance capabilities and the resource efficiency of the GigaNetIC architecture. We show that, if supported by the application, parallelism offers more opportunities than increasing clock frequencies. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1016/j.sysarc.2006.10.007 | Journal of Systems Architecture |
Keywords | Field | DocType |
system on chip,fpga-based rapid prototyping system,rapid prototyping,giganetic,giganetic architecture,multiprocessor architecture,giganoc,asic,general-purpose application,fpga,packet processing application,performance analysis,chip multiprocessor,performance capability,network application scenario,simplifies system verification,firewall application,network on chip,giganetic chip multiprocessor architecture,resource efficiency,hardware accelerator | Space-based architecture,Computer architecture,System on a chip,Computer science,Massively parallel,Parallel computing,Symmetric multiprocessor system,Network on a chip,Packet processing,Reference architecture,Scalability,Embedded system | Journal |
Volume | Issue | ISSN |
53 | 5-6 | Journal of Systems Architecture |
Citations | PageRank | References |
7 | 0.63 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorg Christian Niemann | 1 | 63 | 6.65 |
| Christoph Puttmann | 2 | 36 | 3.90 |
| Mario Porrmann | 3 | 420 | 50.91 |
| U. Rückert | 4 | 755 | 103.61 |