Name
Abstract | ||
|---|---|---|
Information processing and networking of technical devices find their way into our daily life. In order to process the continuously growing quantity of data, powerful communication nodes for network processing are needed. We present an architecture for network processors that is based on a uniform, massively parallel structure. Thus, our approach takes advantage of reusing predefined IP building blocks. This leads to a short time to market, a high reliability and a scalable architecture. Our architecture is scalable to different areas of application by varying the number of integrated processors. Additionally, specific hardware accelerators can be embedded, which are optimized for the target application, in order to be especially resource-efficient in respect to power consumption, computational power and required area. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISVLSI.2005.13 | ISVLSI |
Keywords | Field | DocType |
scalable architecture,network processors,information processing,high reliability,power consumption,daily life,computational power,target application,network processing,parallel soc architecture,different area,network processor,system on chip,switches,spine,computer architecture,system testing,hardware,hardware accelerator,network on a chip | Network processor,Computer architecture,Architecture,Information processing,System on a chip,Massively parallel,System testing,Computer science,Network on a chip,Scalability | Conference |
ISSN | ISBN | Citations |
2159-3469 | 0-7695-2365-X | 14 |
PageRank | References | Authors |
1.10 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorg Christian Niemann | 1 | 63 | 6.65 |
| Mario Porrmann | 2 | 420 | 50.91 |
| Ulrich Ruckert | 3 | 71 | 7.70 |