Paper Info
Title
GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications
Abstract
In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators.
Year
DOI
Venue
2006
10.1007/11682127_19
ARCS
Keywords
Field
DocType
performance analysis,packet processing application,modern cmos standard cell,fpga-based rapid prototyping system,scalable embedded on-chip multiprocessor,network application scenario,simplifies system verification,firewall application,multiprocessor architecture,disparate performance,system concept,hardware accelerator
Applications architecture,Massively parallel,Computer science,Parallel computing,Network architecture,Real-time computing,Packet processing,Hardware acceleration,Standard cell,Systems architecture,Embedded system,Scalability
Conference
Volume
ISSN
ISBN
3894
0302-9743
3-540-32765-7
Citations 
PageRank 
References 
3
0.48
7
Authors
4
Name
Order
Citations
PageRank
Jorg Christian Niemann1636.65
Christoph Puttmann2363.90
Mario Porrmann342050.91
U. Rückert4755103.61