Name
Abstract | ||
|---|---|---|
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clock is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and can achieve small frequency step while maintaining low jitter accumulation. The frequency multiplication part is achieved by using either edge-combing DLL or MDLL structure, while the programmable injection clock is obtained by employing a DLL-based digital-to-phase converter. Based on the proposed architecture, a frequency synthesizer with 50MHz-1.3GHz output frequency tuning range has been design in 0.18μm CMOS technology. And a multiplication ratio of MN / (N+k) can be obtained, in which M, N and K are programmable. The DLL achieves around -42dB reference spur level. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/CCECE.2012.6334833 | CCECE |
Keywords | Field | DocType |
cmos integrated circuits,digital-to-phase converter,frequency 50 mhz to 1.3 ghz,frequency multiplication part,frequency multipliers,edge-combing dll,frequency multiplier,delay-locked loop,multiplication ratio,dll-based digital-to-phase converter,cmos technology,low jitter accumulation,integer-n limitation,frequency synthesizers,mdll structure,programmable injection clock,fractional-n frequency synthesizer,delay lock loops,size 0.18 micron,jitter,multiplexing,delay locked loop | Computer science,Delay-locked loop,Frequency synthesizer,Electronic engineering,Frequency multiplier,CMOS,Multiplication,Jitter,Multiplexing,Computer hardware,Direct digital synthesizer | Conference |
ISSN | ISBN | Citations |
0840-7789 E-ISBN : 978-1-4673-1432-9 | 978-1-4673-1432-9 | 2 |
PageRank | References | Authors |
0.55 | 3 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haizheng Guo | 1 | 3 | 2.65 |
| Tad A. Kwasniewski | 2 | 43 | 13.71 |