Name
Title | ||
|---|---|---|
Network Application Driven Instruction Set Extensions for Embedded Processing Clusters |
Abstract | ||
|---|---|---|
This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processorýs instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance re-evaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/PARELEC.2004.45 | PARELEC |
Keywords | Field | DocType |
instruction set extension,fine-grained performance re-evaluation,extended design,application-specific processor,design automation,instruction pair,performance demand,instruction set,execution performance,set extensions,holistic design methodology,network application driven instruction,electronic design automation,instruction sets,design methodology,embedded systems,chip,application specific integrated circuits,network protocol | Computer architecture,Application-specific instruction-set processor,Instruction set,Computer science,Parallel computing,Compiler,Design methods,Processor design,Electronic design automation,Minimal instruction set computer,Communications protocol | Conference |
ISBN | Citations | PageRank |
0-7695-2080-4 | 10 | 0.89 |
References | Authors | |
4 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Grünewald | 1 | 115 | 10.64 |
| Dinh Khoi Le | 2 | 33 | 3.40 |
| Uwe Kastens | 3 | 406 | 55.65 |
| Jorg Christian Niemann | 4 | 63 | 6.65 |
| Mario Porrmann | 5 | 420 | 50.91 |
| Ulrich Ruckert | 6 | 71 | 7.70 |
| Adrian Slowik | 7 | 39 | 4.03 |
| Michael Thies | 8 | 84 | 10.01 |