Name
Abstract | ||
|---|---|---|
The GigaNetIC project aims to develop high-speed componentsfor networking applications based on massivelyparallel architectures. A central part of this project is thedesign, evaluation, and realization of a parameterizablenetwork processing unit. In this paper we present a designmethodology for network processors which encompassesthe research areas from the application software down tothe gate level of the chip. Key components of this holisticapproach have been successfully applied to characteristicexamples of architecture refinements. |
Year | Venue | Keywords |
|---|---|---|
2003 | LCN | massivelyparallel architecture,application software,high-speed componentsfor networking application,network processor design,central part,architecture refinement,giganetic project,holistic methodology,parameterizablenetwork processing unit,key component,network processor,encompassesthe research area,design methodology,system on chip,complex system,system design,chip |
Field | DocType | ISSN |
Network processor,Computer architecture,Architecture,System on a chip,Network processing unit,Massively parallel,Computer science,Design methods,Chip,Application software,Embedded system | Conference | 0742-1303 |
ISBN | Citations | PageRank |
0-7695-2037-5 | 8 | 1.04 |
References | Authors | |
7 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Olaf Bonorden | 1 | 134 | 9.28 |
| Nikolaus Brüls | 2 | 8 | 1.04 |
| Uwe Kastens | 3 | 406 | 55.65 |
| Dinh Khoi Le | 4 | 33 | 3.40 |
| Friedhelm Meyer auf der Heide | 5 | 1744 | 238.01 |
| Jorg Christian Niemann | 6 | 63 | 6.65 |
| Mario Porrmann | 7 | 420 | 50.91 |
| U. Rückert | 8 | 755 | 103.61 |
| Adrian Slowik | 9 | 39 | 4.03 |
| Michael Thies | 10 | 84 | 10.01 |