Name
Abstract | ||
|---|---|---|
Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip (NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systemson-chip (SoC) design. We proposed an idea on building customizing synthesis network-on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1155/2011/405697 | JOURNAL OF COMPUTER NETWORKS AND COMMUNICATIONS |
Field | DocType | Volume |
% area reduction,Latency (engineering),Computer science,Topology construction,Network topology,Throughput,Interconnection,Embedded system,Power consumption,Scalability | Journal | 2011 |
ISSN | Citations | PageRank |
2090-7141 | 3 | 0.49 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Periyathambi Ezhumalai | 1 | 3 | 0.49 |
| A. Chilambuchelvan | 2 | 7 | 2.96 |
| C. Arun | 3 | 3 | 0.83 |