Name
Abstract | ||
|---|---|---|
Abstract—A 3.2Gbps CDR circuit employs an oversampling architecture to decouple the tradeoff between jitter generation and jitter tolerance. The test chip fabricated in a0.13µmCMOS process achieves a 30x increase in the jitter tolerance corner without increasing recovered clock jitter. Power consumption is 19.5mW from a 1.4V supply at 3.2Gbps and die area is 0.081mm,, . |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405751 | San Jose, CA |
Keywords | Field | DocType |
CMOS digital integrated circuits,clocks,integrated circuit testing,jitter,CMOS process,bit rate 3.2 Gbit/s,jitter generation,jitter tolerance,oversampling CDR,power 19.5 mW,power consumption,recovered clock jitter,size 0.13 mum,test chip,voltage 1.4 V | Oversampling,Computer science,Chip,Cmos process,Electronic engineering,Jitter,Power consumption | Conference |
ISBN | Citations | PageRank |
978-1-4244-1623-3 | 3 | 0.53 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Merrick Brownlee | 1 | 3 | 0.53 |
| Pavan Kumar Hanumolu | 2 | 240 | 27.03 |
| Un-Ku Moon | 3 | 836 | 140.98 |