Paper Info
Title
A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction
Abstract
This paper presents the design and implementation of a high-performance fully-digital PWM DAC and switching output stage which can drive a speaker in portable devices, including cellular phones. Thanks to the quaternary pulse-width modulation scheme, filter-less implementation are possible. A pre-modulation DSP algorithm eliminates the harmonic distortion inherent to the employed modulation process, and an oversampling noise shaper reduces the modulator clock speed to facilitate the hardware implementation while keeping high-fidelity quality. Radiated electromagnetic field emission of the class D amplifier is reduced thanks to a clock spreading technique with only a minor impact on audio performance characteristics. Clock jitter effects on the audio amplifier performance are presented, showing very low degradation for jitter value up to a few nanoseconds. The digital section works with a 1.2 V power supply voltage, while the output switching stage and its driver are supplied from a high-efficiency DC-DC converter either at 3.6 V or 5 V. An output power of 0.5 W at 3.6 V and 1 W at 5 V over an 8 Ω load with efficiency (digital section included) of about 79% and 81%, respectively, has been achieved. The total harmonic distortion (THD) at maximum output level is about 0.2%, while the dynamic range is 104 dB A-weighted. The active area is about 0.94 mm2 in a 0.13 μm single-poly, five-metal, N-well digital CMOS technology with double-oxide option (0.5 μm minimum length).
Year
DOI
Venue
2012
10.1109/JSSC.2011.2178930
Solid-State Circuits, IEEE Journal of
Keywords
Field
DocType
CMOS analogue integrated circuits,DC-DC power convertors,audio-frequency amplifiers,clocks,digital-analogue conversion,electromagnetic interference,harmonic distortion,jitter,power supply circuits,pulse width modulation,EMI reduction,N-well digital CMOS technology,SNR filter-less fully-digital open-loop class D audio amplifier,THD,audio amplifier performance,audio performance characteristics,cellular phones,class D amplifier,clock jitter effects,clock spreading technique,digital section,double-oxide option,filter-less implementation,fully-digital PWM DAC,hardware implementation,high-efficiency DC-DC converter,high-fidelity quality,jitter value,modulation process,modulator clock speed,output switching stage,oversampling noise shaper,portable devices,power 0.5 W,power 1 W,power supply voltage,pre-modulation DSP algorithm,quaternary pulse-width modulation scheme,radiated electromagnetic field emission,size 0.13 mum,switching output stage,total harmonic distortion,voltage 3.6 V,voltage 5 V,Audio amplifiers,EMI,class D amplifiers,harmonic distortion,jitter,noise-shapers,power amplifiers,power-supply intermodulation distortion (PS-IMD),power-supply rejection (PSR),pulse-width modulation (PWM),switching amplifiers
Total harmonic distortion,Class-D amplifier,Oversampling,Computer science,Electromagnetic interference,Pulse-width modulation,Audio power amplifier,Electronic engineering,Jitter,Electrical engineering,Clock rate
Journal
Volume
Issue
ISSN
47
3
0018-9200
Citations 
PageRank 
References 
13
1.10
2
Authors
4
Name
Order
Citations
PageRank
Guanziroli, F.1131.10
Bassoli, R.2131.44
Crippa, C.32116.96
Devecchi, D.4131.78