Power supply noise management continues to be a challenge with the scaling of CMOS technologies. Use of on-chip decoupling capacitors (decaps) is the most common noise suppression technique and has significant associated area and leakage costs. There are numerous methods of implementing decaps and it is not always clear which implementation is the most optimal for the given design constraints. This paper characterizes various decap implementations including MOS-based decaps, multilayer metal decaps, and metal-insulator-metal decaps using postlayout simulations in a 65-nm CMOS technology, and provides an outline for determining the most optimal selection and design of decaps based on area, leakage, and location. Hybrid structures are further shown to boost the area efficiency of conventional nMOS decaps by an additional ∼25%.
VLSI) Systems, IEEE Transactions
Decoupling capacitor (decap),integrated circuit (IC) design,power supply noise
Integrated circuit layout,Capacitor,Noise suppression,NMOS logic,Leakage (electronics),Computer science,Scaling circuits,CMOS,Electronic engineering,Decoupling capacitor