Name
Abstract | ||
|---|---|---|
The occupancy of caches has tended to be dominated by the logic bit value `0' approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value `0' occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategies employing symmetric and asymmetric 6- transistor (6T) and 8T Static Random Access Memory (SRAM) cells. We notice that greater than 38% to 66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM cells based caches. We also study the process variations effect along with NBTI for 32nm and 45nm technology node. It is observed that the rate of recovery in asymmetric SRAM cells based caches is slightly higher than the symmetric and 8T SRAM cells based caches. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DATE.2010.5457137 | Design, Automation & Test in Europe Conference & Exhibition |
Keywords | Field | DocType |
SRAM chips,cache storage,energy conservation,SNM,WNM,negative bias temperature instability,periodic bit flipping,power saving cache strategies,static random access memory | Power saving,Energy conservation,System validation,Cache,Computer science,Parallel computing,Static random-access memory,Real-time computing,Electronic engineering,Negative-bias temperature instability,Transistor,Threshold voltage | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-4244-7054-9 | 22 |
PageRank | References | Authors |
0.87 | 9 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ricketts, A. | 1 | 22 | 0.87 |
| Singh, J. | 2 | 22 | 0.87 |
| Ramakrishnan, K. | 3 | 48 | 4.83 |
| Vijaykrishnan, N. | 4 | 22 | 0.87 |
| Pradhan | 5 | 22 | 0.87 |