Name
Abstract | ||
|---|---|---|
Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum tran... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCAD.2016.2629451 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
FinFETs,Logic gates,Merging,Optimization,Integrated circuits | Transistor count,Logic gate,Diode–transistor logic,Pass transistor logic,Computer science,Electronic engineering,Logic family,Transistor,Integrated circuit,Boolean expression | Journal |
Volume | Issue | ISSN |
36 | 9 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 13 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinicius Neves Possani | 1 | 11 | 3.04 |
| André Inácio Reis | 2 | 134 | 21.33 |
| Renato P. Ribas | 3 | 204 | 33.52 |
| Felipe de Souza Marques | 4 | 34 | 9.47 |
| Leomar Soares da Rosa Jr. | 5 | 8 | 5.35 |