Title
Energy Optimization For Large-Scale 3d Manycores In The Dark-Silicon Era
Abstract
In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V-dd/frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V-dd/frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V-dd/frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V-dd/frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.
Year
DOI
Venue
2019
10.1109/ACCESS.2019.2900477
IEEE ACCESS
Keywords
Field
DocType
3D-stacked chip, dark-silicon, dynamic power, energy-delay-product, frequency scaling, idle power, low-power design, manycore, multicore, process variation, simulator, voltage scaling, voltage selection, within-die variation
Dark silicon,Idle,Simulation,Computer science,Scheduling (computing),Voltage,Ranging,Dynamic demand,Frequency scaling,Energy minimization,Distributed computing
Journal
Volume
ISSN
CitationsĀ 
7
2169-3536
0
PageRankĀ 
ReferencesĀ 
Authors
0.34
0
5
Name
Order
Citations
PageRank
Sohaib Majzoub1204.95
Resve Saleh277161.21
Imran Ashraf337330.26
Mottaqiallah Taouil422433.40
Said Hamdioui5887118.69