Name
Abstract | ||
|---|---|---|
This paper presents a high performance turbo decoder. Its major building blocks, the maximum-a-posteriori decoder and the interleaver, are optimized from architecture to layout level to achieve high-throughput at low-power. This includes a novel architecture for parallel interleaving, that sustains any interleaving scheme. Moreover, the key features of the major building blocks are analyzed and modeled for quick design space exploration e.g. achieving 760Mb/s at 570mW in a 0.13 mu m-CMOS-technology. Finally, the characterized implementations are benchmarked. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ICASSP.2005.1416231 | 2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5: SPEECH PROCESSING |
Keywords | Field | DocType |
integrated circuit layout,throughput,logic design,high throughput,high performance computing,circuits,low power electronics,computer architecture,silicon,turbo codes,cmos technology | Logic synthesis,Integrated circuit layout,Mathematical optimization,Supercomputer,Computer science,Parallel computing,Turbo code,Throughput,Computer hardware,Design space exploration,Interleaving,Low-power electronics | Conference |
ISSN | Citations | PageRank |
1520-6149 | 24 | 1.33 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gordian Prescher | 1 | 24 | 1.33 |
| Tobias Gemmeke | 2 | 49 | 6.49 |
| Tobias G. Noll | 3 | 199 | 37.51 |